Research of Computer Architecture and Parallel Computing

I. Articles in international scientific journals

1. M. Forsell, Are Multiport Memories Physically Feasible?, Computer Architecture News 22, 4 (September 1994), 47-54.

2. M. Forsell, Minimal Pipeline Architecture-an Alternative to Superscalar Architecture, Microprocessors and Microsystems 20, 5 (1996), 277-284.

3. M. Forsell, MTAC—A Multithreaded VLIW Architecture for PRAM Simulation, Journal of Universal Computer Science 3, 9 (1997), 1037-1055.

4. M. Forsell, Cacheless Instruction Fetch Mechanism for Multithreaded Processors, WSEAS Transactions on Communications 1, 1 (2002), 150-155.

5. M. Forsell, Architectural differences of efficient sequential and parallel computers, Journal of Systems Architecture 47, 13 (July 2002), 1017-1041.

(The most downloaded article of Journal of Systems Architecture April - December 2002)

6. M. Forsell, A Scalable High-Performance Computing Solution for Network on Chips, IEEE Micro 22, 5 (September-October 2002), 46-55.

7. E. Ageenko, M. Forsell and P. Fränti, Context-based compression of binary images in parallel, Software: Practice & Experience 32, 13 (November 2002), 1223-1237.

8. M. Forsell, E—A Language for Thread-Level Parallel Programming on Synchronous Shared Memory NOCs, WSEAS Transactions on Computers 3, 3 (July 2004), 807-812.

9. M. Forsell, Realizing constant time parallel algorithms with active memory modules, International Journal of Electronic Business 3, 3-4 (2005), 255-263.

10. M. Forsell, Faster implementation of e for multioperation concurrent read concurrent write MP-SOCs, WSEAS Transactions on Computers 6, 1 (January 2007), 103-110.

11. M. Forsell, On the performance and cost of some PRAM models on CMP hardware, International Journal of Foundations of Computer Science 21, 3 (2010), 387-404.

12. M. Forsell, Performance comparison of some shared memory organizations for 2D mesh-like NOCs, Microprocessors and Microsystems 35, 2 (March 2011), 274-284.

13. M. Forsell, A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads, International Journal of Networking and Computing 1, 1 (January 2011), 21-35.

(Available on-line at http://www.ijnc.org/lib/exe/fetch.php/v01n01p02.pdf)

14. M. Forsell and V. Leppänen, A moving threads processor architecture MTPA, Journal of Supercomputing 57, 1 (2011), 5-19.

II. Scientific monographs and book chapters

15. Martti Forsell, Design and analysis of some chip level parallel architectures, Licentiate thesis, Department of Computer Science, University of Joensuu, Joensuu, 1994.

16. M. Forsell, Implementation of Instruction-Level and Thread-Level Parallelism in Computers, Dissertations 2, Department of Computer Science, University of Joensuu, Joensuu, 1997.

17. M. Forsell, A parallel computer as a NOC region, In Networks on Chip edited by A. Jantsch and H. Tenhunen, Kluver Academic Publishers, Boston, 2003, 173-192.

18. (Hand-out) Proceedings of the Workshop on Highly Parallel Processing on a Chip, edited by M. Forsell and J. Larsson Träff, August 28, 2007, Rennes, France.

19. Euro-Par 2007 Workshops: Parallel Processing, HPPC 2007, UNICORE Summit 2007, and VHPC 2007, edited by L. Bougé, M. Forsell, J. Larsson Träff, A. Streit, W. Ziegler, M. Alexander and S. Childs, Rennes, France, August 28-31, 2007, Revised Selected Papers, Lecture Notes in Computer Science 4854, (2008).

20. (Hand-out) Proceedings of the 2nd Workshop on Highly Parallel Processing on a Chip, edited by M. Forsell and J. Larsson Träff, August 26, 2008, Las Palmas, Spain.

21. (Hand-out) Proceedings of the 3rd Workshop on Highly Parallel Processing on a Chip, edited by M. Forsell and J. Larsson Träff, August 25, 2009, Delft, the Netherlands.

22. M. Forsell, TOTAL ECLIPSE—An Efficient Architectural Realization of the Parallel Random Access Machine, In Parallel and Distributed Computing Edited by Alberto Ros, IN-TECH, Vienna, 2010, 39-64.

23. Euro-Par 2009 — Parallel Processing Workshops: HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, edited by H. Lin, M. Alexander, M. Forsell, A. Knüpfer, R. Prodan, L. Sousa and A. Streit, The Netherlands, August 28-28, 2009, Revised Selected Papers, Lecture Notes in Computer Science 6043, (2010).

24. (Hand-out) Proceedings of the 4th Workshop on Highly Parallel Processing on a Chip, edited by M. Forsell and J. Larsson Träff, August 31, 2010, Ischia - Naples, Italy.

III. Patents and patent applications

25. M. Forsell, Multi-Cell Data Processor, Patent US 7,856,246 B2, December 21, 2010.

IV. Articles in proceedings of international conferences

26. M. Forsell, V. Leppänen and M.Penttonen, Efficient Two-Level Mesh based Simulation of PRAMs, Proceedings of the International Symposium on Parallel Architectures, Algorithms, and Networks, June 12-14, 1996, Beijing, China, 29-35.

27. M. Forsell, Optimal Pipeline Organization for General Purpose Processors, Proceedings of the SSGRR 2001, International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, August 6-12, 2001, L'Aquila, Italy.

28. M. Forsell, Introduction to Concepts in Parallel Computing, Workshop on Systems on Chip, Systems in Package /ESSCIRC 2001, September 17, 2001, Villach, Austria.

29. M. Forsell and S. Kumar, Virtual Distributed Shared Memory for Network on Chip, In the Proceedings of the 19th IEEE NORCHIP Conference, November 12-13, 2001, Kista, Sweden, 192-197.

30. M. Forsell and V. Leppänen, Memory Module Structures for Shared Memory Simulation, In the Proceedings of the SSGRR-2002w, International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet, January 21-27, 2002, L’Aquila, Italy.

31. S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä and A. Hemani, A Network on Chip Architecture and Design Methodology, In the Proceedings of the ISVLSI’02, April 25-26, 2002, Pittsburgh, Pennsylvania, 117-124.

32. J. Soininen, J. Kreku, Y. Qu and M. Forsell, Fast Processor Core Selection for WLAN Modem using Mappability Estimation, In the Proceedings of the 10th International Symposium on Hardware/Software Codesign, May 6-8, 2002, Estes Park, Colorado, USA, 61-66.

33. M. Forsell, Cacheless Instruction Fetch Mechanism for Multithreaded Processors, In the Proceedings of the 6th WSEAS International Conference on Computers, July 7-14, 2002, Rethymnon, Greece, 6761-6766.

34. M. Forsell, Advanced Simulation Environment for Shared Memory Network-on-Chips, In the Proceedings of the 20th IEEE NORCHIP Conference, November 11-12, 2002, Copenhagen, Denmark, 31-36.

35. J. Soininen, J. Kreku, Y. Qu and M. Forsell, Mappability Estimation Approach for Processor Architecture Evaluation, In the Proceedings of the 20th IEEE NORCHIP Conference, November 11-12, Copenhagen, Denmark, 171-176.

36. J. Soininen, A. Pelkonen, J. Kreku, M. Forsell, A. Jantsch and S. Kumar, Extending platform based design to Network on Chip systems, In the Proceedingds of the 16th International Conference on VLSI Design, January 4-8, 2003, New Delhi, India, 401-408.

37. M. Forsell, Using Parallel Slackness for Extracting ILP from Sequential Threads, In the Proceedings of the SSGRR-2003s, International Conference on Advances in Infrastructure for Electronic Business, Education, Science, Medicine, and Mobile Technologies on the Internet, July 28 - August 3, 2003, L’Aquila, Italy.

38. M. Forsell, Analysis of Transport Triggered Architectures in General Purpose Computing, In the the Proceedings of the 21th IEEE NORCHIP Conference, November 10-11, 2003, Riga, Latvia, 183-186.

39. M. Forsell, E—A Language for Thread-Level Parallel Programming on Synchronous Shared Memory NOCs, In the Proceedings of the 3rd WSEAS International Conference on Software Engineering, Parallel & Distributed Systems, February 13-15, 2004, Salzburg, Austria.

40. M. Forsell, Designing NOCs with a parallel extension of c, In the Proceedings of the Forum on specification and Design Languages, September 13-17, 2004, Lille, France, 463-474.

41. M. Forsell, Efficient Barrier Synchronization Mechanism for Emulated Shared Memory NOCs, In the Proceedings of the International Symposium on System-on-Chip 2004, November 16-18, 2004, Tampere, Finland, 33-36.

42. M. Forsell, Ec—A Compiler for the E-Language, In the Proceedings of the International Symposium on System-on-Chip 2004, November 16-18, 2004, Tampere, Finland, 157-160.

43. M.Forsell, Compiling Thread-Level Parallel Programs with a C-Compiler, In the Proceedings of the IV Jornadas sobre Programacion y Lenguajes (PROLE’04), November 11-12, 2004, Malaga, Spain, 215-226.

44. M. Forsell, V. Leppänen, High-Bandwidth on-chip Communication Architecture for General Purpose Computing, In the Proceedings of the 9th World Multiconference on Systemics, Cybernetics and Informatics (WMSCI 2005) Volume IV, July 10-13, 2005, Orlando, USA, 1-6.

45. M. Forsell, Parallel Application Development Scheme for General Purpose NOCs, In the proceedings of the 2005 ECTI International Conference (ECTI-CON 2005), May 12-13, 2005, Pattaya, Thailand, 819-822.

46. M. Forsell, ParLe—A Parallel Computing Learning Set for MPSoCs/NOCs, In the Proceedings of the International Symposium on System-on-Chip 2005, November 15-17, 2005, Tampere, Finland, 90-95.

47. M. Forsell, Step Caches—a Novel Approach to Concurrent Memory Access on Shared Memory MP-SOCs, In the Proceedings of the 23th IEEE NORCHIP Conference, November 21-22, 2005, Oulu, Finland, 74-77.

48. M. Forsell, Reducing the associativity and size of step caches in CRCW operation, In the Proceeding of 8th Workshop on Advances in Parallel and Distributed Computational Models (in conjunction with the 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS´06), April 25, 2006, Rhodes, Greece.

49. M. Forsell, Advances in c-based parallel design of MP-SOCs, In the Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization (SMO'06), September 22-24, 2006, Lisbon, Portugal, 614-621.

50. M. Forsell, Realizing Multioperations for Step Cached MP-SOCs, In the Proceedings of the International Symposium on System-on-Chip 2006 (SOC’06), November 14-16, 2006, Tampere, Finland, 77-82.

51. M. Forsell, A Cost-Efficient Algorithm for Arbitrary CRCW PRAM Simulation, In the Proceedings of the 2007 ECTI International Conference (ECTI-CON 2007), May 9-12, 2007, Chiang Rai, Thailand, 1190-1193.

52. M. Forsell and V. Leppänen, Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC, In the Proceedings of the 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’07), June 25-28, 2007, Las Vegas, USA, 232-238.

53. M. Forsell and J. Träff, HPPC 2007: Workshop on Highly Parallel Processing on a Chip, In Lecture Notes in Computer Science 4854, (2008), 3-4.

54. M. Forsell, On the performance and cost of some PRAM models on CMP hardware, In the Proceedings of the 10th Workshop on Advances in Parallel and Distributed Computational Models (in conjunction with the 22th IEEE International Parallel and Distributed Processing Symposium, IPDPS´08), April 14, 2008, Miami, USA.

55. M. Forsell and J. Träff, HPPC 2008: 2nd Workshop on Highly Parallel Processing on a Chip, In Lecture Notes in Computer Science 5415, (2009), 123-125.

56. M. Forsell and J. Roivainen, Performance, Area and Power Trade-Offs in Mesh-Based Emulated Shared Memory CMP Architectures, In the Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’08), July 14-17, 2008, Las Vegas, USA, 471-477.

57. M. Forsell, Configurable Emulated Shared Memory Architecture for general purpose MP-SOCs and NOC regions, In the Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip, May 10-13, 2009, San Diego, USA, 163-172.

58. M. Forsell, V. Leppänen and M. Penttonen, Challenges of parallel processor design, to appear in the Proceedings of the Annual International Workshop on Advances in Methods of Information and Communication Technology (AMICT’2009), May 19-20, 2009, Petrozavodsk, Russia.

59. J. Paakkulainen, J. Mäkelä, V. Leppänen and M. Forsell, Outline of RISC-based Core for Multicore on Chip Processor Architecture Supporting Moving Threads, In the Proceedings of the CompSysTech’09, June 18-19, 2009, Ruse, Bulgaria.

60. M. Forsell and V. Leppänen, MTPA—A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm, In the proceedings of the 2009 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’09), July 13-16, 2009, Las Vegas, USA, 198-204.

61. M. Forsell, A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads, to appear in the Proceedings of the 12th Workshop on Advances in Parallel and Distributed Computational Models (in conjunction with the 24th IEEE International Parallel and Distributed Processing Symposium, IPDPS’10), April 19, 2010, Atlanta, USA.

62. M. Forsell and J. Träff, HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip, In Lecture Notes in Computer Science 6043, (2010), 3-5.

63. M. Forsell, P. Hofstee, A. Jerraya, C. Jesshope, U. Vishkin and J. Träff, HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?, Lecture Notes in Computer Science 6043, (2010), 9-15.

64. M. Forsell and V. Leppänen, Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs, to appear in the proceedings of the 2010 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’10), July 12-15, 2010, Las Vegas, USA.

65. V. Leppänen, M. Penttonen and M. Forsell, Layouts for Sparse Networks Supporting Throughput Computing, to appear in the proceedings of the 2010 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’10), July 12-15, 2010, Las Vegas, USA.

66. V. Leppänen, M. Forsell and J-M. Mäkelä, Thick Control Flows: Introduction and Prospects, to appear in the Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’11), July 18-21, 2011, Las Vegas, USA, 540-546.

67. V. Leppänen, J-M. Mäkelä and M. Forsell, A RISC-Based Moving Tiny Threads Architecture, to appear in the Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’11), July 18-21, 2011, Las Vegas, USA, 485-491.

68. M. Forsell and J. Roivainen, Supporting Ordered Multiprefix Operations in Emulated Shared Memory CMPs, to appear in the Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’11), July 18-21, 2011, Las Vegas, USA, 506-512.

69. M. Forsell, M. Penttonen and V. Leppänen, Cost of Sparse Mesh Layouts Supporting Throughput Computing, to appear in the Proceedings of EuroMicro Digital Systems Design 2011 (DSD’11), August 31-September 2, 2011, Oulu, Finland.

70. V. Leppänen, M. Penttonen and M. Forsell, A Layout for Sparse Cube-Connected-Cycles Network, to appear in the Proceedings of the CompSysTech'11.

71. J-M. Mäkelä, V. Leppänen and M. Forsell, RISC-based moving threads multicore architecture, to appear in the Proceedings of the CompSysTech'11.

72. M. Forsell and J. Träff, HPPC 2010: Fourth Workshop on Highly Parallel Processing on a Chip, In Lecture Notes in Computer Science 6586, (2011), 73-77.

V. Other scientific publications

73. M. Forsell, Mikroprosessoriarkkitehtuuri (Microprocessor architecture), Masters thesis (in Finnish), Department of Computer Science, University of Joensuu, Joensuu, 1991.

74. M. Forsell, Aksiomaattinen joukko-oppi (Axiomatic Set Theory), Masters thesis (in Finnish), Department of Mathematics, University of Joensuu, Joensuu, 1992.

75. M. Forsell, Are Multiport Memories Physically Feasible? Report A-1993-1, Department of Computer Science, University of Joensuu, Joensuu, 1993.

76. M. Forsell, MPASim - a Simulator for the MPA, Report B-1994-3, Department of Computer Science, University of Joensuu, Joensuu, 1994.

77. M. Forsell, V. Leppänen and M.Penttonen, Efficient Two-Level Mesh based Simulation of PRAMs, Report A-1995-2, Department of Computer Science, University of Joensuu, Joensuu, 1995.

78. M. Forsell, The Minimal Pipeline Architecture, Report A-1995-3, Department of Computer Science, University of Joensuu, Joensuu, 1995.

79. M. Forsell, MTAC—A Multithreaded VLIW Architecture for PRAM Simulation, Report A-1996-7, Department of Computer Science, University of Joensuu, Joensuu, 1996.

80. M. Forsell, MTACSim—a Simulator for the MTAC, Report B-1997-1, Department of Computer Science, University of Joensuu, Joensuu, 1997.

81. M. Forsell, V. Leppänen and M. Penttonen, Primitives of Sequential and Parallel Computation, Report 1998/A/3, Department of Computer Science and Applied Mathematics, University of Kuopio, Kuopio, 1998.

82. E. Ageenko, M. Forsell and P. Fränti, Context-based compression of binary images in parallel, Report A-2000-3, Department of Computer Science, University of Joensuu, Joensuu, 2000.

83. M. Forsell, Architectural differences of efficient sequential and parallel computers, Report A-2000-4, Department of Computer Science, University of Joensuu, Joensuu, 2000.

84. M. Forsell and V. Leppänen, Memory module structures for shared memory simulation, Report A-2000-5, Department of Computer Science, University of Joensuu, Joensuu, 2000.

85. M. Forsell, MemSim - A Memory System Simulator for SDMMs, Report B-2000-1, Department of Computer Science, University of Joensuu, Joensuu, 2000.

86. M. Forsell, Sequential Processor Architecture Research at VTT, In TTA Workshop Notes 2002, Editors J. Lilius and S. Virtanen, TUCS General Publications 21, Turku Centre for Computer Science, Turku, 2002.

87. J. Soininen, M. Forsell and K. Tiensyrjä, Verkkopiirit tulevat—Integroitujen piiriarkkitehtuurien seuraava askel (Networks on chips are coming—The next step of integrated circuit architectures, in Finnish), Prosessori 23, Special Issue on Electronics Design (November 2002), 42-45.

88. M. Forsell, J. Soininen, K. Tiensyrjä, A. Jantsch, K. Kronlöf, and B. Hadjiski, Networks on Chip: Approaches and Challenges, In the Research and Development Activities in Telecommunication Systems 2003, VTT Electronics, Oulu, Finland, 2004, 55-61.

89. M. Forsell, Realizing constant time parallel algorithms with active memory modules, In the Scientific Activities in ICT-sector 2005, VTT, Espoo, 2006, 15-18.

90. M. Forsell, Advances in c-based parallel development of MP-SOCs, In the Scientific Activities in ICT-sector 2006, VTT, Espoo, 2007, 26-28.

91. M. Forsell, Advances in c-based parallel development of MP-SOCs, In the Scientific Activities in ICT-sector 2006, VTT, Espoo, 2007, 26-28.

92. M. Forsell, V. Leppänen and M. Penttonen, Rinnakkaistietokoneen uusi tuleminen, Tietojenkäsittelytiede 28, (Joulukuu2008), 55-65.

VI. Selected scientific presentations

93. M. Forsell, Exploiting parallelism—an essential aspect for future computing, 5th Annual Telecommunication Systems Seminar, August 28, 2003, VTT Electronics, Oulu, Finland.

94. M. Forsell, Massively Parallel Processing on a Chip—Architectural Challenges, In the BOF session on Massively Parallel Processing on a Chip in the 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS´06, April 25-29, 2006, Rhodes, Greece.

95. M. Forsell, Scalable General Purpose CMP Architecture, Scalable Approaches to High-Performance and High-Productivity Computing (ScalPerf’06), September 03-07, 2006, Bertinoro, Italy.

96. M. Forsell, Implementing PRAM on a Chip, Guest lecture for Advanced Parallel Programming: Models, Languages, Algorithms course, March 5, 2007, University of Linköping, Linköping, Sweden.

97. M. Forsell, Performance Issues in Emulated Shared Memory Computing, SaS Division Seminar, March 5, 2007, University of Linköping, Linköping, Sweden.

98. M. Forsell, Parallelism in programming—threat or opportunity?, Keynote talk, Parallel Programming Seminar, November 01, 2007, VTT, Espoo, Finland.

99. M. Forsell, Shared memory chip multiprocessors supporting strong models of computation - The next wave of general purpose parallel computing?, Seminar on future technologies for shared-memory parallel computing, University of Oulu - Oulu Southern Institute, April 29, 2008, Ylivieska, Finland.