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[http://www.ee.oulu.fi/research/tklab/courses/521419A/lab/2005/]
521419A Computer Engineering II: Laboratory Work 2005
This document describes the mandatory pre-lab exercise for the course
Computer Engineering II (521419A) and also gives general information
about the laboratory exercise.
An essential skill of the computer engineering trade is the ability to
read and interpret hardware specifications provided by others. You, as
a student, get to try out the theoretical stuff from lectures in the
laboratory work during this course.
During the laboratory session, you will be given a set of hardware
specifications and a short list of tasks you must perform using the
tools available. The tasks are programming-oriented and it is wise to
get familiar with the available course material before the lab
session.
The pre-lab exercise has been created for your convenience. It
should, for lack of a better word, force you to get familiar with the
subject before doing the actual laboratory work. If you already know a
lot about the subject, the pre-lab exercise should be really easy and
not much of a nuisance. On the other hand, in theory it should give
those with less experience a chance to get familiar with the subject.
The laboratory work will be focused on the Intel x86 architecture and
the tasks consist of programming the peripheral devices in the
PC. You will be using ANSI C and possibly Intel Assembly in the lab.
Laboratory sessions will be held during April in 2005.
You should find a partner and reserve a suitable time from the sign-up
lists. The lists are available in the Optima learning environment.
Pre-lab exercises have to be completed before the laboratory
session. Each group (lab pair) returns one solution, a thoroughly commented
source code file as plaintext via e-mail to the assistants ( t k t 2 - i n
b o x @ e e . o u l u . f i ). Remember to mark both students' names,
years of beginning of the studies and major subjects (TT, ELE, or other) in the
e-mail! Last returning date is one week (five working days) before the
laboratory session. If the returned code does not work it should be
fixed before arriving to the laboratory.
Because the pre-lab exercise may be used as a reference for another program in
the laboratory work, the teams must bring the source code to the
laboratory in a DOS formatted floppy disk.
This year the pre-lab exercise for laboratory work is to write a
program (in ANSI C) that uses the Programmable Interval Timer (PIT)
chip to generate a tone after a short pause.
The delay between starting the program and hearing the tone must be
longer than two seconds, but not longer than three seconds. The tone
must last two seconds. The frequency of the tone must be 900Hz (give
or take a few Hz).
In detail, the resulting program has to...
- override the original timer interrupt routine (at vector 0x8)
- initialize the PIT for suitable timer frequency
- wait until 2 to 3 seconds have passed
- initialize the PIT to produce a tone of given parameters
- let the tone pass through to the internal speaker
- wait until 2 seconds have passed
- block the tone from passing to the internal speaker
- restore the original timer interrupt routine
- end without user invocation
You are not allowed to use the delay(), sleep() or similar functions
from the C library in your solution!
- Hint:
- you may want to write a routine (a function) for producing
variable length delays.
- Hint 2:
-
Remember the common rules of writing an interrupt routine!
8253/8254 PIT - Programmable Interval Timer
Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)
Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)
Port 42h, 8253 Counter 2 Cassette and Speaker Functions
Port 43h, 8253 Mode Control Register, data format:
|7|6|5|4|3|2|1|0| Mode Control Register
| | | | | | | +---- 0=16 binary counter, 1=4 decade BCD counter
| | | | +--------- counter mode bits
| | +------------ read/write/latch format bits
+--------------- counter select bits (also 8254 read back command)
Bits
76 Counter Select Bits
00 select counter 0
01 select counter 1
10 select counter 2
11 read back command (8254 only, illegal on 8253, see below)
Bits
54 Read/Write/Latch Format Bits
00 latch present counter value
01 read/write of MSB only
10 read/write of LSB only
11 read/write LSB, followed by write of MSB
Bits
321 Counter Mode Bits
000 mode 0, interrupt on terminal count; countdown, interrupt,
then wait for a new mode or count; loading a new count in the
middle of a count stops the countdown
001 mode 1, programmable one-shot; countdown with optional
restart; reloading the counter will not affect the countdown
until after the following trigger
010 mode 2, rate generator; generate one pulse after 'count' CLK
cycles; output remains high until after the new countdown has
begun; reloading the count mid-period does not take affect
until after the period
011 mode 3, square wave rate generator; generate one pulse after
'count' CLK cycles; output remains high until 1/2 of the next
countdown; it does this by decrementing by 2 until zero, at
which time it lowers the output signal, reloads the counter
and counts down again until interrupting at 0; reloading the
count mid-period does not take affect until after the period
100 mode 4, software triggered strobe; countdown with output high
until counter zero; at zero output goes low for one CLK
period; countdown is triggered by loading counter; reloading
counter takes effect on next CLK pulse
101 mode 5, hardware triggered strobe; countdown after triggering
with output high until counter zero; at zero output goes low
for one CLK period
Read Back Command Format (8254 only)
|7|6|5|4|3|2|1|0| Read Back Command (written to Mode Control Reg)
| | | | | | | +--- must be zero
| | | | | | +---- select counter 0
| | | | | +----- select counter 1
| | | | +------ select counter 2
| | | +------- 0 = latch status of selected counters
| | +-------- 0 = latch count of selected counters
+----------- 11 = read back command
Read Back Command Status (8254 only, read from counter register)
|7|6|5|4|3|2|1|0| Read Back Command Status
| | | | | | | +--- 0=16 binary counter, 1=4 decade BCD counter
| | | | +-------- counter mode bits (see Mode Control Reg above)
| | +----------- read/write/latch format (see Mode Control Reg)
| +------------ 1=null count (no count set), 0=count available
+------------- state of OUT pin (1=high, 0=low)
- the 8253 is used on the PC & XT, while the 8254 is used on the AT+
- all counters are decrementing and fully independent
- the PIT is tied to 3 clock lines all generating 1.19318 MHz.
- the value of 1.193180MHz is derived from (4.77/4 MHz) and has it's
roots based on NTSC frequencies
- counters are 16 bit quantities which are decremented and then
tested against zero. Valid range is (0-65535). To get a value
of 65536 clocks you must specify 0 as the default count since
65536 is a 17 bit value.
- reading by latching the count doesn't disturb the countdown but
reading the port directly does; except when using the 8254 Read
Back Command
- counter 0 is the time of day interrupt and is generated
approximately 18.2 times per sec. The value 18.2 is derived from
the frequency 1.19318/65536 (the normal default count).
- counter 1 is normally set to 18 (dec.) and signals the 8237 to do
a RAM refresh approximately every 15.s
- counter 2 is normally used to generate tones from the speaker
but can be used as a regular counter when used in conjunction
with the 8255
- the output from counter 2 of is directed to the PC speaker if
the 2 LSBs of the register at address 0x61 are set to 1
- newly loaded counters don't take effect until after a an output
pulse or input CLK cycle depending on the mode
- the 8253 has a max input clock rate of 2.6MHz, the 8254 has max
input clock rate of 10MHz
Programming considerations:
1. load Mode Control Register
2. let bus settle (jmp $+2)
3. write counter value
4. if counter 0 is modified, an INT 8 handler must be written to
call the original INT 8 handler every 18.2 seconds. When it
does call the original INT 8 handler it must NOT send and EOI
to the 8259 for the timer interrupt, since the original INT 8
handler will send the EOI also.
Example code:
countdown equ 8000h ; approx 36 interrupts per second
cli
mov al,00110110b ; bit 7,6 = (00) timer counter 0
; bit 5,4 = (11) write LSB then MSB
; bit 3-1 = (011) generate square wave
; bit 0 = (0) binary counter
out 43h,al ; prep PIT, counter 0, square wave&init count
jmp $+2
mov cx,countdown ; default is 0x0000 (65536) (18.2 per sec)
; interrupts when counter decrements to 0
mov al,cl ; send LSB of timer count
out 40h,al
jmp $+2
mov al,ch ; send MSB of timer count
out 40h,al
jmp $+2
sti
8259 Programmable Interrupt Controller (PIC)
Initialization Command Word 1 at Port 20h and A0h
|7|6|5|4|3|2|1|0| ICW1
| | | | | | | +---- 1=ICW4 is needed, 0=no ICW4 needed
| | | | | | +----- 1=single 8259, 0=cascading 8259's
| | | | | +------ 1=4 byte interrupt vectors, 0=8 byte int vectors
| | | | +------- 1=level triggered mode, 0=edge triggered mode
| | | +-------- must be 1 for ICW1 (port must also be 20h or A0h)
+------------- must be zero for PC systems
Initialization Command Word 2 at Port 21h and A1h
|7|6|5|4|3|2|1|0| ICW2
| | | | | +-------- 000= on 80x86 systems
+----------------- A7-A3 of 80x86 interrupt vector
Initialization Command Word 3 at Port 21h and A1h
|7|6|5|4|3|2|1|0| ICW3 for Master Device
| | | | | | | +---- 1=interrupt request 0 has slave, 0=no slave
| | | | | | +----- 1=interrupt request 1 has slave, 0=no slave
| | | | | +------ 1=interrupt request 2 has slave, 0=no slave
| | | | +------- 1=interrupt request 3 has slave, 0=no slave
| | | +-------- 1=interrupt request 4 has slave, 0=no slave
| | +--------- 1=interrupt request 5 has slave, 0=no slave
| +---------- 1=interrupt request 6 has slave, 0=no slave
+----------- 1=interrupt request 7 has slave, 0=no slave
|7|6|5|4|3|2|1|0| ICW3 for Slave Device
| | | | | +-------- master interrupt request slave is attached to
+----------------- must be zero
Initialization Command Word 4 at Port 21h and A1h
|7|6|5|4|3|2|1|0| ICW4
| | | | | | | +---- 1 for 80x86 mode, 0 = MCS 80/85 mode
| | | | | | +----- 1 = auto EOI, 0=normal EOI
| | | | +-------- slave/master buffered mode (see below)
| | | +--------- 1 = special fully nested mode (SFNM), 0=sequential
+-------------- unused (set to zero)
Bits
32 Buffering Mode
00 not buffered
01 not buffered
10 buffered mode slave (PC mode)
11 buffered mode master (PC mode)
Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h)
|7|6|5|4|3|2|1|0| OCW1 - IMR Interrupt Mask Register
| | | | | | | +---- 0 = service IRQ0, 1 = mask off
| | | | | | +----- 0 = service IRQ1, 1 = mask off
| | | | | +------ 0 = service IRQ2, 1 = mask off
| | | | +------- 0 = service IRQ3, 1 = mask off
| | | +-------- 0 = service IRQ4, 1 = mask off
| | +--------- 0 = service IRQ5, 1 = mask off
| +---------- 0 = service IRQ6, 1 = mask off
+----------- 0 = service IRQ7, 1 = mask off
Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h)
|7|6|5|4|3|2|1|0| OCW2 - ICR Interrupt Command Register
| | | | | +-------- interrupt request level to act upon
| | | | +--------- must be 0 for OCW2
| | | +---------- must be 0 for OCW2
+--------------- EOI type (see table)
Bits
765 EOI - End Of Interrupt code (PC specific)
001 non-specific EOI command
010 NOP
011 specific EOI command
100 rotate in automatic EOI mode
101 rotate on non-specific EOI command
110 set priority command (uses bits 2-0)
111 rotate on specific EOI command
Operation Control Word 3 (Ports 20h & A0h)
|7|6|5|4|3|2|1|0| OCW3
| | | | | | | +--- 1=read IRR on next read, 0=read ISR on next read
| | | | | | +---- 1=act on value of bit 0, 0=no action if bit 0 set
| | | | | +----- 1=poll command issued, 0=no poll command issued
| | | | +------ must be 1 for OCW3
| | | +------- must be 0 for OCW3
| | +-------- 1=set special mask, 0=reset special mask
| +--------- 1=act on value of bit 5, 0=no action if bit 5 set
+---------- not used (zero)
Other Registers
IRR - Interrupt Request Register, maintains a bit vector indicating
which IRQ hardware events are awaiting service. Highest
level interrupt is reset when the CPU acknowledges interrupt.
ISR - In Service Register, tracks IRQ line currently being serviced.
Updated by EOI command.
Hardware Interrupt Sequence of Events:
1. 8259 IRQ signal is raised high by hardware setting the
corresponding IRR bits true.
2. PIC evaluates the interrupt requests and signals the CPU
where appropriate.
3. CPU acknowledges the INT by pulsing INTA (inverted)
4. INTA signal from CPU is received by the PIC, which then sets the
highest priority ISR bit, and clears the corresponding IRR bit
5. CPU sends a second INTA pulse which causes the PIC to send the
interrupt ID byte onto the bus. CPU begins interrupt processing.
6. Interrupts of lower and equal priority are blocked until a
Non-Specific EOI (20h) is sent to the command port.
Initialization Procedure
Initialization
1. write ICW1 to port 20h
2. write ICW2 to port 21h
3. if ICW1 bit D1=1 do nothing
if ICW1 bit D1=0 write ICW3 to port 20h
4. write ICW4 to port 21h
5. OCW's can follow in any order
8259 Programmable Interrupt Controller Notes
- Operation Command Word (OCW), commands that set the 8259 in
various interrupt modes. These can be written to the 8259
anytime after initialization.
- The 8259 differentiates between the OCW1, OCW2 and OCW3 by the
port address and the value of the data bits D4 and D3. ICW2
through ICW4 are order related and must follow ICW1. ICW1 is
identified by an even port number and data bit D4 set to 1.
- PCs operate in fully nested mode, where a Non-Specific EOI resets
the interrupt identified by the highest bit value in the ISR
- 8259s can be chained together where the INT pin (output) of a
slave 8259 can be used as the input to an IRQ line allowing up
to 64 priority vectored interrupts. AT level machines use two
8259's for a total of 16 hardware interrupt levels
- the first 8259 ports are located at 20h and 21h
- the second 8259 ports are located at A0h and A1h
- PC and AT interrupts are Edge Triggered while PS/2's are Level
Triggered
- some ASIC chips designed for Tandy 1000 Systems malfunction if
specific and non-specific EOIs are mixed
- for a more in-depth discussion of the 8259, see Intel's "Micro-
processor and Peripherals Handbook, Volume I"
- see PORTS and INT TABLE
The laboratory sessions are held in the computer class TS135. The work
is done in pairs with standard PC machines, Windows operating system,
Borland C compiler and VT-100 terminal.
This year's laboratory material and solutions to the tasks are available in
a ZIP package.
If you have questions about the laboratory work please feel free to
contact teaching assistants. See the
main
page for details.
[http://www.ee.oulu.fi/research/tklab/courses/521419A/lab/2005/]
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