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Electrical and Information Engineering

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PROBLEM 2.1(4-1)

Show the block diagram of the hardware that implements the following register transfer statement:

yTs : R2 <- R1, R1 <- R2


This simultaneous operation is possible with registers that have edge-triggered flip-flops. The registers are connected to each other and the signal from the AND-gate serves as LD (load) signal.

PROBLEM 2.2(4-3)

Represent the following conditional control statement by two register transfer statements with control functions.

If (P = 1) then (R1 <- R2) else if (Q = 1) then (R1 <- R3)


P : R1 <- R2 ; If (P = 1) then (R1 <- R2)

P'Q : R1 <- R3 ; else if (Q = 1) the (R1 <-R3)

PROBLEM 2.3(4-2)

The outputs of four registers, R0, R1, R2, and R3, are connected through 4-to-1-line multiplexers to the inputs of a fifth register, R5. Each register is eight bits long. The required transfers are dictated by four timing variables T0 through T3 as follows:

T0: R5<-R0

T1: R5<-R1

T2: R5<-R2

T3: R5<-R3

The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5.


4 registers => 4 x 1 line multiplexer

8 bits / register => 8 multiplexers

The desired multiplexer is selected with the help of the encoder logic. If any of the timing variables is set, the LD signal to R5 is activated.

PROBLEM 2.4(4-4)

What has to be done to the bus system of fig. 4-3 to be able to transfer information from any register to any other register? Specifically, show the connections that must be included to provide a path from the outputs of register C to the inputs of register A.


The registers A, B,C and D must be replaced with registers that have edge triggered flip-flops. LD signals to the registers determine the register receiving the information. Specifically, in the figure below the register A is enabled by a LD (load) signal.

PROBLEM 2.5(4-5)

Draw a diagram of a bus system similar to the one shown in Fig. 4-3, but use three-state buffers (see Fig. 4-4) and a decoder instead of the multiplexers.


The S1 and S2 control signals are decoded so that only one of the outputs of the decoder is active at a time. This way, only one group of the 3-state buffers is passing the (normal) input they receive. As a result, the contents of the registers are passed on correctly.

PROBLEM 2.6(4-6)

A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.

a) How many selection inputs are there in each multiplexer?

b) What size of multiplexers are needed?

c) How many multiplexers are there in the bus?


a) 16 registers = 24 => 4 selection inputs

b) 16 registers => 16 x 1 line multiplexers

c) 32 bits / register => 32 multiplexers

PROBLEM 2.7(4-9)

Show the hardware that implements the following statement. Include the logic gates for the control function and a block diagram for the binary counter with a count enable input.

xyT0 + T1 + y'T2: AR<-AR + 1


The left "side" of the picture is trivial. Information is loaded from a bus to AR (address register) and when the output of the control logic is 1, AR is incremented (INR) at the next rising of the clock signal. This information is the passed on (AR has clear (CLR) and load (LD) inputs as well).

PROBLEM 2.8(4-10)

Consider the following register transfer statements for two 4-bits registers R1 and R2.

xT: R1<-R1 + R2

x'T: R1<-R2

Every time that variable T=1, either the content of R2 is added to the content of R1 if x=1, or the content of R2 is transferred to R1 if x=0.

Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two 4-bit registers, a 4-bit adder, and a quadruple 2-to-1line multiplexer that selects the inputs to R1. In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1.


The variable T serves as a load signal to R1, because it (T) must be enabled in order to the circuit to do anything. R1 + R2 and R2 are the inputs of the mux. The output of the mux is selected according to the logic table and is directed to the register R1.

Appendix 1

Figure 4-3

Figure 4-4

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